Research associates (m/f/x)

Aufgaben

• Architectural Research and NPU Innovation: Research and formulate novel bitwise, systolic dot-product array architectures capable of dynamically switching quantization bit-widths (multi-precision) and approximate computing (AxC) units at runtime. Investigate internal microarchitectures, command stream-based control mechanisms, and architectural protection primitives.
• Prototyping and System-Level Research: Embed the NPU core into a full SoC platform (including RISC-V CPUs, AXI interconnects, and peripherals). Perform research-driven Design Space Explorations (DSE) and Power, Performance, and Area (PPA) analyses under realistic application workloads.
• Silicon Realization and Physical Validation: Bridge academic theory with physical realization by preparing verified RTL frontends and IP documentation for a 22nm GlobalFoundries ASIC tapeout. Perform post-silicon validation and characterization to benchmark physical chip measurements against theoretical models.
• HW/SW Co-Design and Algorithmic Exploration: Conduct fundamental research on the interplay between dynamic precision scaling, model accuracy, and system resilience. Develop novel algorithms and co-design strategies to embed hardware guarantees (e.g. regarding real-time, security, or accuracy) directly into NN models.
• Scientific Dissemination: Publish research findings in top-tier international peer-reviewed EDA, computer architecture, and hardware design conferences and journals.
• Research Ownership: Take ownership of your PhD research topic, formulate and test original scientific hypotheses, and work independently while collaborating with academic and industrial consortium partners.

Profil

• Excellent Master’s degree in computer science, electrical engineering, computer engineering, or a related field.
• Strong scientific curiosity and background in computer architecture, digital frontend design (RTL, e.g., SystemVerilog), or HW/SW co-design.
• High motivation to conduct independent doctoral research and publish at premier international venues.
• Strong interest or preliminary experience in machine learning hardware accelerators (NPUs), approximate computing, or fault-tolerant design.
• Practical familiarity with standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, AMD/Xilinx Vivado, or comparable tools) and enthusiasm for physical silicon realization (tapeout).
• Broad, interdisciplinary mindset capable of abstracting system constraints across the entire hardware/software stack.
• Excellent interpersonal skills for collaborative research, along with fluency in English (written and oral).
• Ability to take responsibility for advancing complex research and development topics.
• Experience in industrial R&D, chip design, or EDA toolflows is an advantage.

Erweiterte Kenntnisse: Programmiersprache Verilog, Synopsys

Rahmenbedingungen

Scope: full-time
Duration: fixed-term, 3 years
Start: starting January 1st, 2027